1. Field of the Invention
The present invention relates to a semiconductor apparatus and, in particular, to a semiconductor apparatus for use in a low voltage power supply.
2. Description of the Related Art
As an example of a semiconductor integrated circuit whose circuit characteristics largely vary corresponding to the fluctuation of a voltage of power supply, a PLL (Phase Locked Loop) circuit is known. The PLL circuit that compensates the circuit operation against the fluctuation of the voltage of power supply has been disclosed, for example, in Japanese Patent Laid-Open Publication No. 4-167815.
Next, with reference to FIG. 14, the PLL circuit of the related art reference will be described. A phase comparator 1 that operates at a first power supply voltage 105 compares the phase of an input signal 101 with the phase of an output signal 104 of a voltage controlling oscillator 3 and outputs a first phase error signal 102. A constant voltage generator 4 inputs a second power supply voltage 107 and outputs a constant voltage 108 to a gate circuit 5.
The gate circuit 5 inputs the first phase error signal 102 and outputs a second phase error signal 106 to a low pass filter 2. The low pass filter 2 outputs an averaged control voltage signal 103 to the voltage controlling oscillator 3. The voltage controlling oscillator 3 inputs the control voltage signal 103 and outputs an output signal 104 to the phase comparator 1.
In this structure, when the first power supply voltage 105 that is input to the phase comparator 1 fluctuates, the first phase error signal 102 which is the output signal of the phase comparator 1 also fluctuates. However, when the voltage 108 that is output from the constant voltage generator 4 is constant, the voltage of the second phase error signal 106 that is output from the gate circuit 5 is kept constant.
Thus, since the second phase error signal 106 is averaged by the low pass filter 2, the voltage of the control signal 103 that is output from the low pass filter 2 does not fluctuate. In addition, the oscillation frequency of the voltage controlling oscillator 3 does not also fluctuate. As a result, a PLL circuit that is not affected by the fluctuation of the first power supply voltage 105 can be accomplished.
In the conventional PLL circuit, when the phase comparator 1 is composed of transistors, as the first power supply voltage 105 becomes lower, the operation speed of the transistors that compose the phase comparator 1 decreases. Thus, the phase error accuracy determined by the phase comparator 1 deteriorates. Even if the power supply voltage of the gate circuit 5 is supplied from the constant voltage generator 4 that is a constant power supply, when the frequency of the input signal 101 that is input to the phase comparator 1 exceeds a predetermined value, the phase comparator 1 does not follow the input signal 101. Thus, the PLL circuit malfunctions.
In addition, since the constant voltage generator 4 does not have a voltage raising function, when the second power supply voltage 107 that is input to the constant voltage generator 4 drops, the constant voltage generator 4 cannot output the gate circuit power supply voltage 108 required by the gate circuit 5. Thus, it is difficult to use the conventional PLL circuit with a low voltage power supply.